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litex_setup.py : submodules fail to sync when restoring frozen sha1 or tag

Status: Open.

#2430 In enjoy-digital/litex;

· Tomserv-512 opened on Mar 10, 2026

Boot failed using the latest branch of LiteX with Vexiiriscv

Status: Open.

#2429 In enjoy-digital/litex;

· looongbin opened on Mar 9, 2026

Attempt to build basic project for slogic16u3 board (GW5AT fpga) ends with an error

Status: Open.

#2428 In enjoy-digital/litex;

· rgerty opened on Mar 8, 2026

SD-Card does not function as intended after loading the FPGA from the SD-Card

Status: Open.

#2419 In enjoy-digital/litex;

· KunoTV opened on Feb 25, 2026

Platforms/targets with two ETH

Status: Open.

#2416 In enjoy-digital/litex;

· ermachkov opened on Feb 11, 2026

How should the bus configuration in the vexii litex integration be handled?

Status: Open.

#2401 In enjoy-digital/litex;

· cklarhorst opened on Jan 13, 2026

Can't extract CSR name from code in Python 3.14

Status: Open.

#2399 In enjoy-digital/litex;

· david-sawatzke opened on Jan 13, 2026

litex_bare_metal_demo not starting on VexiiRiscv@Nexys4

Status: Open.

#2392 In enjoy-digital/litex;

· KunoTV opened on Jan 7, 2026

M-Labs is leaving GitHub

Status: Open.

#2388 In enjoy-digital/litex;

· sbourdeauducq opened on Jan 3, 2026

support cocotb+verilator for sim

Status: Open.

#2380 In enjoy-digital/litex;

· DavisLiu1989 opened on Dec 5, 2025

float C computing on VexRiscV and global custom_app process

Status: Open.

#2378 In enjoy-digital/litex;

· PJfixer opened on Dec 3, 2025

SoC : add AXI master output

question

Status: Open.

#2377 In enjoy-digital/litex;

· PJfixer opened on Dec 2, 2025