ip-core

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🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation

template opensource asic hardware systemverilog ip-core openlane hardware-ip vyges silicon-design

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

python vhdl verification vip pip verilog systemverilog ip-core rtl-design

Python-based IP-XACT parser

asic fpga xml eda spirit rtl asciidoc ip verilog ip-xact soc vlsi uvm ip-core design-automation accellera ieee-1685 ieee1685

A Python-based IP Core Management Infrastructure.

infrastructure database simulation vhdl intel python3 xilinx synthesis altera modelsim questasim xilinx-vivado quartus-prime vhdl-verification ip-core riviera-pro

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